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CAT34RC02
2-kb I2C Serial EEPROM, Serial Presence Detect FEATURES
I 400 kHz I2C bus compatible* I 1.7 to 5.5 volt operation I 16-byte page write buffer I Hardware write protection for entire memory I Permanent and reversible software write I Schmitt trigger on SCL and SDA inputs I Low power CMOS technology I 1,000,000 program/erase cycles I 100 year data retention I 8-pin TSSOP and TDFN packages I Industrial temperature range
protection for lower 128 bytes
DESCRIPTION
The CAT34RC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each. Catalyst's advanced CMOS technology substantially reduces device power requirements. The CAT34RC02 features
a 16-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin TSSOP and TDFN packages.
PIN CONFIGURATION
TDFN Package (SP2, VP2)
A0 1 A1 2 A2 3 VSS 4
8 VCC 7 WP 6 SCL 5 SDA
TSSOP Package (U, Y, GY)
A0 A1 A2
PIN FUNCTIONS
Pin Name A0, A1, A2 SDA SCL WP VCC VSS
D
VSS
is
1 2 3 4
o c
8 7 6 5
i t n
VCC WP SCL SDA
u n
FUNCTIONAL SYMBOL
VCC
d e
a P
t r
SCL
A2, A1, A0 WP
CAT34RC02
SDA
VSS
Function
Device Address Inputs Serial Data/Address Serial Clock Write Protect 1.7 V to 5.5 V Power Supply Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 1052, Rev. O
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CAT34RC02
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55C to +125C Storage Temperature ........................ -65C to +150C Voltage on Any Pin with Respect to Ground(1) ............ -2.0 V to VCC + 2.0 V Voltage on A0 .................................................. -2.0 V to +12.0 V VCC with Respect to VSS .............................. -2.0 V to +7.0 V RELIABILITY CHARACTERISTICS(2) Symbol NEND
(*)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention ESD Susceptibility Latch-up
Min 1,000,000 100 4000 100
Program/ Erase Cycles Years Volts mA
TDR(*) VZAP(*) ILTH
(3)
(*) Page Mode, VCC = 5 V, 25C
D.C. OPERATING CHARACTERISTICS
VCC = 1.7 V to 5.5 V, unless otherwise specified.
Symbol ICC ICC ISB(4) ILI ILO VIL VIH VOL1 VOL2 VHV
Parameter Power Supply Current (Read) Power Supply Current (Write)
Test Conditions
Standby Current (VCC = 5.0 V) Input Leakage Current Output Leakage Current Input Low Voltage
Input High Voltage
CAPACITANCE TA = 25C, f = 400 kHz, VCC = 5 V Symbol CI/O(2) CIN
(2)
ZWPL ZWPH
is D
Output Low Voltage (VCC = 3.0 V) Output Low Voltage (VCC = 1.7 V) RSWP Set/Clear Overdrive A0 High Voltage
o c
Test
i t n
fSCL = 100 kHz fSCL = 100 kHz
VIN = GND or VCC VIN = GND to VCC
VOUT = GND to VCC
u n
d e
Min -1 7 Min
a P
Max 1 3 1 1 1 VCC x 0.3 VCC + 1.0 0.4 0.5 10
Units
t r
Units mA mA A A A V V V V V
Typ
VCC x 0.7
IOL = 3 mA
IOL = 1.5 mA
VHV - VCC > 4.8 V
Conditions VI/O = 0 V VIN = 0 V VIN < 0.5 V VIN > VCC x 0.7
Typ
Max 8 6
Units pF pF k k
Input/Output Capacitance (SDA) Input Capacitance (other pins) WP Input Impedance WP Input Impedance
5 500
70
Note: (1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -2.0 V or overshoot to no more than VCC + 2.0 V, for periods of less than 20 ns. The maximum DC voltage on address pin A0 is +12.0 V. (2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (3) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1.0 V to VCC + 1.0 V. (4) Standby Current, ISB = 10 A max at extended temperature range.
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT34RC02
A.C. CHARACTERISTICS
VCC = 1.7 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits Symbol Parameter 1.7 V - 5.5 V Min FSCL TI(1) tAA tBUF(1) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(1) tF
(1)
2.5 V - 5.5 V Min Max 400 100 Units
Max 100 100 3.5
Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time 4.7 4 4.7 4 4.7
1.3 0.6
SDA and SCL Rise Time SDA and SCL Fall Time
tSU:STO tDH
Stop Condition Setup Time Data Out Hold Time
Power-Up Timing(1)(2) Symbol tPUR tPUW
Write Cycle Limits Symbol tWR
is D
Power-up to Read Operation Power-up to Write Operation
o c
Parameter Parameter
i t n
u n
0 250 4 100
1
d e
1.3 0.6 0.6 0 100 0.6 100 Typ
a P
0.3 300 Max 1 1
0.9
t r
ns s s s s s s ns ns s ns s ns
kHz
300
Min
Units ms ms
Min
Typ
Max 5
Units ms
Write Cycle Time
The write cycle time is the time elapsed between the STOP command (following the write instruction) and the completion of the internal write cycle. During the internal
write cycle, SDA is released by the Slave and the device does not acknowledge external commands.
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1052, Rev. O
CAT34RC02
FUNCTIONAL DESCRIPTION
The CAT34RC02 supports the I2C (2-wire) Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT34RC02 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or receiver, but the Master alone assigns those roles. A maximum of 8 devices may be connected to the bus as determined by the device address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL: Serial Clock The serial clock input pin is used to clock all data transfers into or out of the device. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer data into and out of the device. This pin is an open drain output in transmit mode. A0, A1, A2: Device Address Inputs These inputs set the device address. When left floating, the address pins are internally pulled to ground. WP: Write Protect
This input, when grounded or left floating, allows write operations to the entire memory. When this pin is tied to VCC, the entire memory is write protected. Figure 1. Bus Timing
tF tLOW SCL tSU:STA tHD:STA tHIGH tLOW tR
SDA IN
tAA SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
Figure 3. Start/Stop Timing
D
is
SDA SCL
o c
8th Bit Byte n
i t n
tHD:DAT
u n
tDH
tSU:DAT
d e
a P
tSU:STO tBUF
t r
ACK tWR STOP CONDITION START CONDITION ADDRESS
START BIT
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STOP BIT
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
4
CAT34RC02
I2C BUS PROTOCOL
The I2C bus consists of two `wires', SCL and SDA. The two `wires' are connected to the supply (VCC) via pull-up resistors. Master and Slave devices connect to the bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to `transmit' a `0' and releases it to `transmit' a `1'. (1) Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). (2) During a data transfer, the data line must remain stable whenever the SCL line is high. An SDA transition while SCL is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START condition acts as a `wake-up' call for the Slave devices. A Slave will not respond to commands unless the MASTER generates a START condition. STOP Condition The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP condition starts the internal write cycle, when following a WRITE command and sends the Slave into standby mode, when following a READ command.
Device Addressing The Master initiates a data transfer by creating a START condition on the bus. The Master then broadcasts an 8bit serial Slave address. The four most significant bits of the Slave address (the `preamble') are fixed to 1010 (Ah), for normal read/write operations and 0110 (6h) for Software Write Protect (SWP) operations (Fig. 5). The next three bits, A2, A1 and A0, select one of eight possible Slave devices. The last bit, R/W, specifies whether a Read (1) or Write (0) operation is to be performed. Acknowledge
Figure 4. Acknowledge Timing
Figure 5. Slave Address Bits
is D
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER
o c
SCL FROM MASTER
i t n
1
u n
After processing the Slave address, the Slave responds with an acknowledge (ACK) by pulling down the SDA line during the 9th clock cycle. The Slave will aslo acknowledge the 8-bit byte address and every data byte presented in WRITE mode. In READ mode the Slave shifts out eight bits of data, and then `releases' the SDA line durng the 9th clock cycle. If the Master acknowledges in the 9th clock cycle (by pulling down the SDA line), then the Slave continues transmitting. When data transfer is complete, the Master responds with a NoACK (it does not acknowledge the last data byte) and the Slave stops transmitting and waits for a STOP condition.
d e
8
a P
9
t r
START
ACKNOWLEDGE
1
0
1
0
A2
A1
A0
R/W
Normal Read and Write
DEVICE ADDRESS 0 1 1 0 A2 A1 A0 R/W Programming the Write Protect Register
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1052, Rev. O
CAT34RC02
WRITE OPERATIONS
Byte Write In Byte Write mode the Master creates a START condition, and then broadcasts the Slave address, byte address and data to be written. The Slave acknowledges the three bytes by pulling down the SDA line during the 9th clock cycle following each byte. The Master creates a STOP condition after the last ACK from the Slave, which then starts the internal write operation (Fig. 6). During internal write, the Slave will ignore any read/write request from the Master. Page Write The CAT34RC02 contains 256 bytes of data, arranged in 16 pages of 16 bytes each. The page is selected by the four most significant bits of the address byte presented to the device after the Slave address, while the four least significant bits point to the byte within the page. By `loading' more than one data byte into the device, up to an entire page can be written in one write cycle (Fig. 7). The internal byte address counter will increment after each data byte. If the Master transmits more than 16 data bytes, then earlier bytes will be overwritten by later bytes in a `wrap-around' fashion within the selected page. The internal write cycle is started following the STOP condition created by the Master. Acknowledge Polling
acknowledge the Slave address, as long as internal write is in progress.
WRITE PROTECTION
Hardware Write Protection With the WP pin held HIGH, the entire memory, as well as the SWP flags are protected against WRITE operations (Fig. 9). If the WP pin is left floating or is grounded. then it has no impact on the operation of the CAT34RC02. Software Write Protection
Acknowledge polling can be used to determine if the CAT34RC02 is busy writing or is ready to accept commands. Polling is implemented by sending a `Selective Read' command (described under READ OPERATIONS) to the device. The CAT34RC02 will not
Figure 6. Byte Write Timing
Figure 7. Page Write Timing
BUS ACTIVITY: MASTER SDA LINE S T A R T S A C K SLAVE ADDRESS * A C K A C K A C K A C K BYTE ADDRESS (n) S T O P P
D
is
BUS ACTIVITY: MASTER SDA LINE
o c
S T A R T S
i t n
SLAVE ADDRESS A C K
u n
BYTE ADDRESS A C K
The lower half of memory (first 128 bytes) can be protected against WRITE operations by setting one of two Software Write Protection (SWP) flags/switches. The PSWP (Permanent Software Write Protection) flag can be set but not cleared by the user. The RSWP (Reversible Software Write Protection) flag can be set and cleared by the user. Whereas the PSWP flag can be set `in-system', the RSWP flag is meant to be used during testing. RSWP commands require the presence of a very high voltage (higher than VCC) on address pin A0 and fixed logic levels for the other two address pins.
The CAT34RC02 is shipped `unprotected'. The state of the SWP flags can be read by issuing an `Immediate Address Read' command, with the Slave address `preamble' set to 0110 (6h) instead of the `normal' 1010 (Ah). A SWP READ will return the complemented versions of the two flags in the last two slots of the resulting data byte; the other six more significant bits in the data byte have no meaning to the user (Fig. 11).
d e
DATA
a P
t r
S T O P P A C K
DATA n
DATA n+1
DATA n+P
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT34RC02
The PSWP flag can be set (forever) by issuing a `Byte Write' command, with the Slave address preamble set to `6h', followed by a `don't care' address, followed by `don't care' data and a STOP condition. The CAT34RC02 will acknowledge the Slave address, dummy byte address and dummy data (Fig. 10). The PSWP flag will be permanently set (after the internal write cycle is completed). The SWP commands are shown in Table 1. Table 1. SWP Commands
command attempts to `reaffirm' one of the two switches, then the CAT34RC02 will not acknowledge the command itself. In addition, the CAT34RC02 will not acknowledge a `reaffirming' SWP command, even if the WP pin is LOW. Power-On Reset (POR) The CAT34RC02 incorporates Power-On Reset (POR) circuitry which protects the device against malfunctioning while VCC is lower than the recommended operating voltage. The device will power up into a read-only state and will power-down into a reset state when VCC crosses the POR level of ~1.3V.
Slave Address PIN Command SWP READ RSWP SET RSWP CLEAR PSWP SET A2 A2 0 0 A2 A1 A1 0 1 A1 A0 A0 VHV VHV A0 B7 0 0 0 0 Preamble B6 1 1 1 1 B5 1 1 1 1 B4 0 0 0 0 Device Address B3 A2 0 0 A2 B2 A1 0 1 A1 B1 A0 1 1 A0 R/W W B0 1 0 0 0
READ OPERATIONS
Immediate Address Read
The CAT34RC02 will not acknowledge RSWP or PSWP commands, once the PSWP flag is set. If the PSWP flag is not set, but the WP pin is HIGH, then the CAT34RC02 will react to RSWP or PSWP commands as follows: if the command attempts to `flip' one of the two SWP switches, then the CAT34RC02 will respond the same way the regular memory would, i.e. the command and address (in this case dummy) are acknowledged, but the data (in this case dummy) will not be acknowledged; if the Figure 8. Immediate Address Read Timing
D
is
o c
i t n
S T A R T S 8 8th Bit
u n
A C K
In standby mode, the CAT34RC02 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If the `previous' byte was the last byte in memory, then the address counter will point to the first memory byte, etc. If the CAT34RC02 decodes a Slave address with a `1' in the R/W bit position (Fig. 8), it will issue an ACK in the 9th clock cycle, and will then transmit the data byte being pointed at by the address counter. The Master can then stop further transmission by issuing a NoACK, followed by a STOP condition. Selective Read The READ operation can also be started at an address different from the one stored in the address counter. The
d e
S T O P P N O A C K
a P
t r
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
DATA
SCL
9
SDA
DATA OUT
NO ACK
STOP
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1052, Rev. O
CAT34RC02
address counter can be `initialized' by performing a `dummy' WRITE operation (Fig. 12). The START condition is followed by the Slave address (with the R/W bit set to `0') and the desired byte address. Instead of following up with data, the Master then issues a 2nd START, followed by the `Immediate Address Read' sequence, as described earlier.
Sequential Read If the Master acknowledges the 1st data byte transmitted by the CAT34RC02, then the device will continue transmitting as long as each data byte is acknowledged by the Master (Fig. 13). If the end of memory is reached during sequential READ, the address counter will `wraparound' to the beginning of memory, etc. Sequential READ works with either `Immediate Address Read' or `Selective Read', the only difference being the starting byte address.
Figure 9. Memory Array
FFH
7FH
Hardware Write Protectable (by connecting WP pin to Vcc)
00H
Figure 10. Software Write Protect (Write)
S T A R T
BUS ACTIVITY: MASTER
* For PSWP A0 is at normal CMOS levels and for RSWP, A0 is at VHV which must be held high beyond the end of the STOP condition (approximately 1s of "overlap" is sufficient).
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SDA LINE S
i t n
SLAVE ADDRESS A C K
u n
BYTE ADDRESS A C K X = Don't Care
Software Write Protectable (by setting the write protect flags)
d e
DATA XXXXXXXX A C K S T O P P
a P
t r
XXXXXXXX
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT34RC02
Figure 11. Software Write Protect (Read)
RSWP S T O P P N O A C K
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
PSWP
000000 A C K DATA
Figure 12. Selective Read Timing
S T A R T S A C K A C K S T A R T S
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS
BYTE ADDRESS (n)
SLAVE ADDRESS
Figure 13. Sequential Read Timing
BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS
D
is
o c
A C K
DATA n
i t n
A C K
u n
A C K
d e
A C K
A C K
a P
S T O P P DATA n N O A C K
DATA n+x
t r
DATA n+1
DATA n+2
S T O P P N O A C K
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1052, Rev. O
CAT34RC02
8-PAD TDFN 2X3 PACKAGE (VP2, SP2)
A
E
PIN 1 INDEX AREA
D
A2
SYMBOL A A1 A2 A3 b D D2 E E2 e K L
MIN 0.70 0.00 0.45
NOTE: 1. ALL DIMENSIONS IN MM. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMNALS. COPLANARITY SHALL NOT EXCEED 0.08 MM. 3. WARPAGE SHALL NOT EXCEED 0.10 MM. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE NOT CONSIDERED AS SPECIAL CHARACTERISTIC.
TDFN2X3_(02).eps
D
is
0.18 1.90 1.27 2.90 1.23 0.20 0.30
o c
NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 3.00 0.50 TYP 0.40
MAX 0.80 0.05 0.65 0.30 2.10 1.75 3.10 1.90
i t n
A3
u n
E2 b
d e
D2
a P
A1 K
t r
PIN 1 ID
L
0.50
3xe
e
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT34RC02
8-LEAD TSSOP (U, Y, GY)
3.0 + 0.1 -A8 5
7.72 TYP
6.4 4.4 + 0.1 -B(1.78 TYP) 3.2
4.16 TYP
0.42 TYP 0.2 C B A 1
PIN #1 IDENT.
4
ALL LEAD TIPS
LAND PATTERN RECOMMENDATION
1.1 MAX TYP
0.1 C
ALL LEAD TIPS
-C-
0.65 TYP
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0.19 - 0.30 TYP 0.3 M A B S C S
i t n
(0.9)
0.10 + 0.05 TYP
u n
0-8
o o
d e
0.6+0.1
0.65 TYP
SEE DETAIL A
a P
t r
0.09 - 0.20 TYP
GAGE PLANE 0.25
SEATING PLANE
DETAIL A
Notes: 1. Lead coplanarity is 0.004" (0.102mm) maximum.
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1052, Rev. O
CAT34RC02
ORDERING INFORMATION
Prefix CAT Device # 34RC02 J Suffix I TE13 REV-E
Company ID
Product Number
Temperature Range I = Industrial (-40C to +85C)
Die Revision 34RC02: E
Package U: TSSOP Y: TSSOP (Lead-free, Halogen-free) SP2: TDFN VP2: TDFN (Lead-free, Halogen-free) GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
Tape & Reel
Notes: (1) The device used in the above example is a CAT34RC02UI-TE13 REV E (TSSOP, Industrial Temperature, 1.7 Volt to 5.5 Volt Operating Voltage, Tape & Reel)
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT34RC02
REVISION HISTORY
Date 09/22/03 12/09/03 01/12/04 Revision Comments A B C Initial Issue Removed Automotive temperature range Changed Industrial Temp to " I" from " Blank" in ordering information Updated Features Replaced Block Diagram with Functional Symbol Updated Notes for Reliability Characteristics, D.C. Operating Characteristics and Capacitance Updated TDFN package Updated packaging information to reflect new TDFN package Re-labeled TDFN package to A0, A1, A2 instead of A1, A2, A3 Updated Absolute Max. Ratings Updated DC Operating Characteristics Updated Table 1 (SWP Commands) Updated Fig 11 Added mechanical package drawings Corrected TDFN drawing Corrected table 1 SWP Commands Update Update Update Update D.C. Operating Characteristics Write Cycle Limits Revision History Rev Number
02/20/04 03/22/04
D E
03/31/04 05/16/04
F G
06/03/04
H
Update Die Revision in Ordering Information Eliminate data sheet designation Updated DC Operating Characteristics Updated Write Cycle Limits
06/07/04 9/27/04 10/18/04 1/11/05 2/17/05 07/19/05
I J K L M N
Added Power-On Reset (POR) description Added VHV and deleted VHV in DC Operating Characteristics Updated DC Operating Characteristics & notes (removed Note 5) Deleted DIP and SOIC packages in all areas Deleted Extended temperature range in all areas
Update Reliability Characteristics table and notes Update Ordering Information
08/05/05
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 1052, Rev. O
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Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.caalyst-semiconductor.com
Publication #: Revison: Issue date:
1052 O 08/05/05

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